VLSI@NU

[DAC]Shiyu Guo, Yuhao Ju, Xi Chen, Jie Gu, LLM-MARK: A Computing Framework on Efficient Watermarking of Large Language Models for Authentic Use of Generative AI at Local Devices, Design Automation Conference (DAC), 2024.
[ISSCC]Yuhao Ju, Ganqi Xu, Jie Gu, A 28nm Physics Computing Unit Supporting Emerging Physics-informed Neural Network and Finite Element Method for Real-time Scientific Computing on Edge Devices, International Solid-State Circuit Conference (ISSCC), 2024. (pdf)
[ISSCC]Yijie Wei, Zhiwei Zhong, Lance Go, Jie Gu, A Sub 1 uJ/class Headset-integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-purpose Instruction Set Architecture, International Solid-State Circuit Conference (ISSCC), 2024. (pdf)
[ISSCC]Shiyu Guo, Sachin Sapatnekar, Jie Gu, A 28nm Physical-based Ray-Tracing Rendering Processor for Photorealistic Augmented Reality with Inverse Rendering and Background Clustering for Mobile Devices, International Solid-State Circuit Conference (ISSCC), 2024. (pdf)
[VLSI]Qiankai Cao, Juin Oh, Jie Gu, A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics, VLSI Symposium on Circuits and Technology (VLSI), 2024. (pdf)
[ISLPED]Qiankai Cao, Xi Chen, Jie Gu, Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning , International Symposium on Low Power Electronics Design (ISLPED), 2023.
[VLSI Symp]Yuhao Ju, Yijie Wei, Xi Chen, Jie Gu, A General-Purpose Compute-in-Memory Processor Combining CPU and Deep Learning with State-of-the-art CPU Efficiency and Enhanced Data Locality, VLSI Symposium on Circuits and Technology (VLSI), 2023.(pdf)
[VLSI Symp]Yijie Wei, Xi Chen, Jie Gu, Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classification and Chained Infrared Communication for Multi-chip Collaboration, VLSI Symposium on Circuits and Technology (VLSI), 2023.(pdf)
[VLSI Symp]Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang, Raveesh Magod, Nachiket Desai, Jie Gu, Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs, VLSI Symposium on Circuits and Technology (VLSI), 2023.(pdf)
[CICC]Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang, Raveesh Magod, Nachiket Desai, Jie Gu, A 65nm Fully-integrated Fast-switching Buck Convertr with Resonant Gate Drive and Automatic Tracking, Custom Integrated Circuit Conference (CICC), 2023.(pdf)
[JSSC (invited)]Yuhao Ju, Jie Gu, A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing with Enhanced Data Locality and End-to-End Performance, Journal of Solid-State Circuits (JSSC), 2023.(pdf)
[VLSI Symp]Qiankai Cao, Jie Gu, A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management, VLSI Symposium on Circuits and Technology (VLSI), 2022.(pdf)
[ESSCIRC]Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu, A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement, European Solid-State Circuit Conference (ESSCIRC), 2022.(pdf)
[DAC]Yijie Wei, Zhiwei Zhong, Jie Gu, Human Emotion Based Real-time Memory and Computation Management on Resource-Limited Edge Devices, Design Automation Conference (DAC), 2022.
[CICC]Yijie Wei, Xi Chen, Jie Gu, A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition, Custum Integrated Circuit Conference (CICC), 2022.
[ISSCC]Yuhao Ju, Jie Gu, A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance, International COnfererence on Solid-state Circuits (ISSCC), 2022. (pdf)
[JSSC]Yijie Wei, Qiankai Cao, Kofi Otseidu, Levi Hargrove, Jie Gu, A Gesture Classification SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Training Capable Neural Network Classifier, Journal of Solid-state Circuits (JSSC), 2021.
[ISSCC]Zhengyu Chen, Xi Chen, Jie Gu, A 65nm 3T Dynamic Analog RAM Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhance, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency, International Solid-state Circuit Conference (ISSCC), 2021.
[ADFM]Vinod K. Sangwan, Jie Gu, Mark C. Hersam, et al., Visualizing Thermally Activated Memristive Switching in Percolating Networks of Solution-Processed 2D Semiconductors, Advanced Functional Materials, 2021.
[ICCAD]Hadi Esmaeilzadeh, Soroush Ghodrati, Shiyu Guo, Jie Gu, Andrew Kahng, Sachin Sapatnekar, et.al, VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis, International Conference on Computer-Aided Design (ICCAD), 2021.
[VLSI Symp]Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu, A Mixed-signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-signal On-chip Training for Low Power Edge Devices, Symposia on VLSI Technology and Circuit, 2020. (pdf)
[ISSCC]Tianyu Jia, Yuhao Ju, Jie Gu, A Compute-adaptive Elastic Clock Chain Technique with Dynamic Timing Enhancement for 2D PE Array Based Accelerators, International Solid-state Circuit Conference (ISSCC), 2020. (pdf)
[DAC]Yijie Wei, Kofi Otseidu, Jie Gu, Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-low Power SoC, Design Automation Conference (DAC), 2020. (pdf)
[MICRO]Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu, NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance, Microarchitecture (MICRO), 2020. (pdf)
[CICC]Yijie Wei, Kofi Otseidu, Qiankai Cao, Levi Hargrove, Jie Gu, A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training, Custom Integrated Circuits Conference (CICC), 2020. (pdf)
[JSSC]Zhengyu Chen, Jie Gu, High-throughput Dynamic Time Warning Accelerator for Time-Series Classification with Pipelined Mixed-signal Time-domain Computing, Journal of Solid-State Circuits (JSSC), In Press.
[JSSC, Invited]Tianyu Jia, Yuhao Ju, Jie Gu, A Dynamic Time Enhanced DNN Accelerator with Compute-Adaptive Elastic Clock Chain Technique, Journal of Solid-State Circuits (JSSC), 2020.
[EMBC]Yijie Wei, Qiankai Cao, Levi Hargrove, Jie Gu, A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collabrative Neural Network Classifier for Low Dimensional Data Communication, International Conferences of IEEE Engineering in Medicine and Biology Society (EMBC), 2020.
[DAC]Zhengyu Chen, Hai Zhou, Jie Gu, Digital Compatible Synthesis, Placement and Implementation of Mixed-signal Time-domain Computing, Design Automation Conference (DAC), 2019.(pdf)
[ISSCC]Zhengyu Chen, Jie Gu, A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput, International Solid-state Circuit Conference (ISSCC), 2019. (pdf)
[ISSCC]Tianyu Jia, Russ Joseph, Jie Gu, An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution,International Solid-state Circuit Conference (ISSCC), 2019. (pdf)
[ISVLSI]Amin Rezaei, Jie Gu, Hai Zhou, Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries (ISVLSI), 2019.
[JSSC]Tianyu Jia, Russ Joseph, Jie Gu, An Instruction Driven Adaptive Clock Management Through Dynamic Phase Scaling and Cross-Layer Design Assistance for a Low Power Microprocessor, Journal of Solid-State Circuits, 2019.
[JSSC]Zhengyu Chen, Jie Gu, A Time-domain Computing Accelerated Image Recognition Processor with Efficient Time Encoding and Non-linear Logic Operation, Journal of Solid-State Circuits, 2019.
[TVLSI]Zhengyu Chen, Hai Zhou, Jie Gu, R-Accelerator: A RRAM Based CGRA Accelerator with Logic Contraction, IEEE Transactions on VLSI Systems, 2019.
[ASSCC]Tianyu Jia, Jie Gu, A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications, Asian Solid-State Circuit Conference, 2018.
[DAC]Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph, Compiler-guided Instruction-level Clock Scheduling for Timing Speculative Processor, Design Automatoin Conference, 2018.
[ESSCIRC]Tianyu Jia, Russ Joseph, Jie Gu, An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor, European Solid-state Circuits Conference (ESSCIRC), 2018.
[DATE]A Rezaei, Y Shen, S Kong, Jie Gu, Hai Zhou, Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks, Design, Automatoin & Test in Europe Conference & Exhibition (DATE), 2018.
[ICCD]Zhengyu Chen, Hai Zhou, Jie Gu, R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing, International Conference on Computer Design (ICCD), 2018.
[JSSC] Tianyu Jia, Jie Gu, A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications, IEEE Journal of Solid-State Circuits, 2018.
[TVLSI]Shuyu Kong, Hai Zhou, Jie Gu, Design and Synthesis of Self-healing Memrisive Circuits for Timing Resilient Processor Design, IEEE Transactions on VLSI Systems, 2018.
[TVLSI]Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu, A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage Scalable Design, IEEE Transactions on VLSI Systems, 2018.
[VLSI Symposium]Tianyu Jia, Jie Gu, A 0.3-0.86V Fully Integrated Buck Regulator with 2GHz Resonant Switching for Ultra-Low Power Applications, VLSI Symposium on Circuits, 2017.(pdf)
[DAC]Tianyu Jia, Russ Joseph, Jie Gu, Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management, Design Automation Conference (DAC), 2017. (pdf)
[ASP-DAC]Yang You, Jie Gu, Exploiting Accelerated Aging Effect for On-line Configurability and Hardware Tracking, ASP-DAC, 2017.
[ISCAS]Yingyi Luo, Jie Gu, Seda Ogrenci-Memik, Cell-to-Array Thermal-Aware Analysis of Stacked RRAM, ISCAS, 2017.
[ISVLSI]Shuyu Kong, Jie Gu, Hai Zhou, Memristor-Based Clock Design and Optimization with In-situ Tunability, ISVLSI, 2017.
Tianyu Jia, Jie Gu, Switched Capacitor Regulator Modeling and Optimization for Instruction-based Ultra-fine Dynamic Voltage Scaling (IUDVS), ICCAD Workshop, 2016.
[DAC]Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu, Exploration of Associative Power Management with Instruction Governed Operation for Ultra-low Power Design, Design Automation Conference (DAC), 2016.
[ISLPED]Zhengyu Chen, Jie Gu, Analysis and Design of Energy Efficient Time Domain Signal Processing, International Symposium on Low Power Electronic Design (ISLPED), 2016.
[ISLPED]Huanyu Wang, Geng Xie, Jie Gu, Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design, International Symposium on Low Power Electronic Design (ISLPED), 2016.
[ISCAS]Jie Gu, Jieda Li, Self-healing Circuits for Timing Resilient Design Using Emerging Memristor Devices, International Symposium on Circuits and Systems (ISCAS), 2015.
[VLSI Design]Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan, Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations, VLSI Design, 112-117, 2012
[DATE]Rahul Rithe, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan, Non-Linear Operating Point Statistical Analysis for Local Variations in Logic Timing at Low Voltage, Design Automation and Test in Europe Conference (DATE), March 2010.
[ISSCC]Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko, A 28nm 0.6V low-power DSP for mobile applications, International Solid-State Circuit Conference (ISSCC), pp. 132-134, Feb. 2011.
[CICC]Dong Jiao, Jie Gu, Chris Kim, Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise, Custom Integrated Circuit Conference (CICC), Sept. 2009.
[ISLPED]Dong Jiao, Jie Gu, P. Jain, and Chris Kim, "Enhancing Benefitical Jitter Using Phase-Shifted Clock Distribution", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2008.
Pingqiang Zhou, Jie Gu, Pulkit Jain, Chris Kim, and Sachin S. Sapatnekar, Reliable Power Delivery for 3D ICs, Sematech Workshop on Design and Test Challenges for 3D ICs, 2008.
[VLSI Symposium]Jie Gu, Hanyong Eom, Chris Kim, A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping, Symposium on VLSI Circuits, pp.126-127, Japan, Jun. 2007.
[ISLPED]Jie Gu, Hanyong Eom, Chris Kim, Sleep Transistor Sizing and Control for Resonant Supply Noise Damping, International Symposium on Low Power Electronics and Design, pp. 80-85, Portland, Aug. 2007.
[VLSI Symposium]Jie Gu, Ramesh Harjani, Chris Kim, Distributed Active Decoupling Capacitor Circuits for On-Chip Power Supply Regulation in Digital VLSI Circuits, Symposium on VLSI Circuits, pp. 216-217, Hawaii, Jun. 2006.
[DAC]Jie Gu, Sachin Sapatnekar, Chris Kim, "Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift", Design Automation Conference (DAC), pp.87-92, San Diego, Jun.2007.
[CICC]Jie Gu, John Keane, Sachin Sapatnekar, Chris Kim, Width Quantization Aware FinFET Circuit Design, Custom Integrated Circuit Conference, pp. 337-340, San Jose, Sep. 2006.
[ISLPED]Jie Gu, Chris Kim, Study and Analysis of Leakage Induced Damping Effect in Low Voltage LSIs, International Symposium on Low Power Electronics and Design, pp. 382-387, Germany, Oct. 2006.
[ISLPED]Jie Gu, Chris Kim, "Multi-Level Power Delivery for Supply Noise Reduction and Low Voltage Operation", International Symposium on Low Power Electronics and Design, pp. 192-197, San Diego, Aug. 2005.
[ISLPED]Jonggab Kil, Jie Gu, Chris Kim, "A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting", International Symposium on Low Power Electronics and Design, pp. 67-72, Germany, Oct. 2006.
Chad R. Barry, Aaron M. Welle, Jie Gu, Stephen A. Campbell and Heiko O. Jacobs, "Printing of Nanoparticles with Sub-100nm Resolution," Proc. NSF CMMI Grantees Conference, Scottsdale, AZ, 2005.
Jie Gu, C. R. Barry and H. O. Jacobs, "NanoXerography: The Directed Self-Assembly of Nanoparticle Building Blocks onto Charged Based Receptors," Proc. 7th International Conference on Nanostructured Materials, 2004.

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