Jie Gu, Ph.D
Assistant Professor | Principle Investigator
Department of Electrical and Computer Engineering
Tech Inst. Room L473
McCormick School of Engineering and Applied Sciences
2145 Sheridan Road
Evanston, IL 60208-311
(847) 467 5854
(847) 467 1492
- CurrentWe are looking for PhD students or postdoc researchers to join us in 2020.
Congratulate to Yuhao Ju and Tianyu Jia for winning best poster award in the recent IBM IEEE AI Compute Symposium with a novel Neural CPU architecture. Refer to the news report from eetimes .
Congratulate Zhengyu, Xi on our paper acceptance into ISSCC'21. For the first time, a CMOS "analog RAM" is designed to accelerate CNN operation in a Compute-in-Memory design with record-breaking performance.
Congratulate Tianyu, Yuhao on paper acceptance into Microachitecture (MICRO) conference. A unique neural network based RISC-V architecture was demonstrated with silicon test chip showing significant performance and cost benefits.
Congratulate Tianyu Jia for receiving Best PhD Dissertation Award in ECE Department!!!
Congratulate Zhengyu Chen, Sihua Fu, Qiankai Cao on the acceptance of the mixed-signal Generative Adversarial Network (GAN) accelerator into Symposia of VLSI Technology and Circuits 2020.
Our team member Yijie Wei presented a tiny gesture-sensing chip with embedded distributed neural network classifier and online training capability for biomedical rehabilitation applications in CICC conference. This is the first chip with fully integrated analog front end and deep neural network classifier for the goal of getting advaned AI into wearable devices.
Congratulate Tianyu Jia for receiving ISSCC Predoctoral Achievement Award!!!
Our paper on CNN accelerator with compute-adaptive clocking technique is accepted into ISSCC 2020. Congratulations to Tianyu Jia and Yuhao Ju.
Prof. Gu gave a talk in Argonne National Lab on acceleration of modern computing tasks using emerging circuit techniques.
Prof. Gu received the prestigious NSF Career Award.
Zhengyu Chen presented our design methodology for time domain circuits in this year's Design Automation Conference (DAC).
Tianyu Jia and Zhengyu Chen join Apple and Google for summer internship. Congratulations.
We have two papers accepted into ISSCC'19 including a time-domain dynamic time warping accelerator design and an GPU design with instruction driven ultra-dynamic clock scaling. Congratulations to Zhengyu Chen and Tianyu Jia.
We hosted a nationwide diversity workshop for minority students. More information is in circuit & architecture summer school . We thank NU, CRA-W, Intel's generous support and all the invited speakers. The workshop received overwhemingly positive feedback from each attendee. Hopefully, we will do it again soon.
We delivered an interesting work on distributed neural network design
for biomedical physiological signal processing. With built-in machine
learning capability, the edge processing device consumes only
micro-Watts power and can communicate with each other for collaborated
neural network operation.
Jie Gu gave a workshop talk at International Conerence on Computer
Aided Design (ICCAD) Workshop, titled: "Let a Program Touch the
Transistors: a Cross-layer Design Methodology for Co-design and
Collaboration between Microprocessor and Mixed-Signal Circuits".
Jie Gu gave an invited talk at Midwest Symposium on Circuits and
Systems (MWSCAS), titled: "Software-Guided Greybox Design Methodology
with Integrated Power and Clock Management".
delivered the world's fastest regulator running at 2GHz with a special
resonant switching technique for Ultra-low Voltage/ Near-threshold
- 6/2017Tianyu Jia published
the paper "A 0.3-0.86V Fully Integrated Buck Regulator with 2GHz
Resonant Switching for Ultra-Low Power Applications", at 2017 Symposia
on VLSI Technology and Circuits (Kyoto, Japan).
Jia presented the paper "Greybox Design Methodology: A Program Driven
Hardware Co-optimization with Ultra-Dynamic Clock Management", at
Design Automation Conference (DAC) 2017.
- 5/2017Prof. Gu gave a talk in Greater Chicago Area System Research Workshop (GCASR).
Jie Gu presented the paper "Exploiting Accelerated Aging Effect for
On-line Configurability and Hardware Tracking", at ASP-DAC 2017.
Jie Gu gave a talk at International Conerence on Computer Aided Design
(ICCAD) Workshop, titled: "Switched Capacitor Regulator Modeling and
Optimization for Instruction-based Ultra-fine Dynamic Voltage Scaling
- 10/2016Our first test chip "Emma" just came back in October and it works !!!
- 09/2016Kofi Otseidu joined the group as Ph.D. student.
- 08/2016Zhengyu Chen presented the Paper "Analysis and Design of Energy Efficient Timing domain signal processing" at ISLPED 2016.
Wang presented the paper "Comprehensive Analysis, Modeling and Design
for Hold-Timing Resiliency in Voltage Scalable Design" at ISLPED 2016.
Jia presented the paper "Exploration of Associative Power Management
with Instruction Governed Operation for Ultra-low Power Design" at DAC