For a complete list of publications, please see publication page.
- [VLSI symposium]
Tianyu Jia, Jie Gu, A 0.3-0.86V Fully Integrated Buck Regulator with
2GHz Resonant Switching for Ultra-Low Power Applications, VLSI
Symposium on Circuits, 2017.
Jia, Russ Joseph, Jie Gu, Greybox Design Methodology: A Program Driven
Hardware Co-optimization with Ultra-Dynamic Clock Management, Design
Automation Conference (DAC), 2017.
- [ASP-DAC]Yang You, Jie Gu, Exploiting Accelerated Aging Effect for On-line Configurability and Hardware Tracking, ASP-DAC, 2017.
Jia, Yuanbo Fan, Russ Joseph, Jie Gu, "Exploration of Associative Power
Management with Instruction Governed Operation for Ultra-low Power
Design", Design Automation Conference (DAC), 2016.
Chen, Jie Gu, "Analysis and Design of Energy Efficient Time Domain
Signal Processing", International Symposium on Low Power Electronic
Design (ISLPED), 2016.
Wang, Geng Xie, Jie Gu, "Comprehensive Analysis, Modeling and Design
for Hold-Timing Resiliency in Voltage Scalable Design", International
Symposium on Low Power Electronic Design (ISLPED), 2016.
Gu, Jieda Li, Self-healing Circuits for Timing Resilient Design Using
Emerging Memristor Devices, International Symposium on Circuits and
Systems (ISCAS), 2015.