Welcome to VLSI Research Lab at Northwestern University

Group News

• CurrentWe are looking for PhD students or postdoc researchers to join us in 2025.
• 2/2024 We gave a live demonstration on EEG controlled VR scene for mind/motor imagery with intelligent neural interface to ISSCC'24. Please see our demonstration videos.
• 2/2024 Congratulations to Shiyu Guo for a paper accepted into DAC'2024.
• 12/2023 Congratulations to our students Yuhao Ju and Yijie Wei for winning the honorable SSCS predoctoral achievement awards.
• 10/2023 Three papers have been accepted into ISSCC'24. Congratulate to every group member.
• 9/2023 Congratulate to Xi Chen, the new groom in our group!!! Best wishes to your new journey of happiness and love.
• 7/2023 Congratulate to Qiankai for publishing into ISLPED conference on a novel time-domain tropical algebraic low power circuit design.
• 6/2023 Congratulate to Qiankai, the new groom in our group!!! Wish you a long, happy life with the one you love.
• 4/2023 Three papers are accepted into the prestigious VLSI Symposium'23. Congratulate to Yuhao, Xi, Yijie and all the authors. Special thanks to our collaborators Xin Zhang from IBM, Raveesh Magod from TI, and Nachiket Desai from Intel.
• 1/2023 Congratulate to Xi for the acceptance into CICC'23 on the resonant gate drive based power converters.
• 5/2022 Congratulate to Yuhao, Shiyu, Zixuan and Tianyu for the acceptance into ESSCIRC'22 on the first logic reasoning IC chip.
• 3/2022 Congratulate to Qiankai for the acceptance into VLSI Symposium'22 on the first 3D/4D point-cloud sparse convolution accelerator chip for AR/VR applications.
• 2/2022 Congratulate to Yijie and Zhiwei for the acceptance into DAC'22 on the exploration of emotion based memory and computing management.
• 1/2022 Congratulate to Yijie and Xi for the acceptance into CICC'22 on the wireless powered biomedical SoC with data and weight compression for efficient on-chip neural network accelerator.
• 10/2021 Congratulate to Yuhao Ju for his acceptance into ISSCC'22 on his new version of "Neural CPU", a combined deep learning and RISC-V architecture.
• 1/2021 Congratulate to Yuhao Ju and Tianyu Jia for winning best poster award in the recent IBM IEEE AI Compute Symposium with a novel Neural CPU architecture. Refer to the news report from eetimes .
• 10/2020 Congratulate Zhengyu, Xi on our paper acceptance into ISSCC'21. For the first time, a CMOS "analog RAM" is designed to accelerate CNN operation in a Compute-in-Memory design with record-breaking performance.
• 08/2020 Congratulate Tianyu, Yuhao on paper acceptance into Microachitecture (MICRO) conference. A unique neural network based RISC-V architecture was demonstrated with silicon test chip showing significant performance and cost benefits.
• 05/2020 Congratulate Tianyu Jia for receiving Best PhD Dissertation Award in ECE Department!!!
• 04/2020 Congratulate Zhengyu Chen, Sihua Fu, Qiankai Cao on the acceptance of the mixed-signal Generative Adversarial Network (GAN) accelerator into Symposia of VLSI Technology and Circuits 2020.
• 03/2020 Our team member Yijie Wei presented a tiny gesture-sensing chip with embedded distributed neural network classifier and online training capability for biomedical rehabilitation applications in CICC conference. This is the first chip with fully integrated analog front end and deep neural network classifier for the goal of getting advaned AI into wearable devices.
• 02/2020 Congratulate Tianyu Jia for receiving ISSCC Predoctoral Achievement Award!!!
• 10/2019 Our paper on CNN accelerator with compute-adaptive clocking technique is accepted into ISSCC 2020. Congratulations to Tianyu Jia and Yuhao Ju.
• 8/2019 Prof. Gu gave a talk in Argonne National Lab on acceleration of modern computing tasks using emerging circuit techniques.
• 6/2019 Prof. Gu received the prestigious NSF Career Award.
• 6/2019 Zhengyu Chen presented our design methodology for time domain circuits in this year's Design Automation Conference (DAC).
• 5/2019 Tianyu Jia and Zhengyu Chen join Apple and Google for summer internship. Congratulations.
• 10/2018 We have two papers accepted into ISSCC'19 including a time-domain dynamic time warping accelerator design and an GPU design with instruction driven ultra-dynamic clock scaling. Congratulations to Zhengyu Chen and Tianyu Jia.
• 8/2018 We hosted a nationwide diversity workshop for minority students. More information is in circuit & architecture summer school . We thank NU, CRA-W, Intel's generous support and all the invited speakers. The workshop received overwhemingly positive feedback from each attendee. Hopefully, we will do it again soon.
• 6/2018 We delivered an interesting work on distributed neural network design for biomedical physiological signal processing. With built-in machine learning capability, the edge processing device consumes only micro-Watts power and can communicate with each other for collaborated neural network operation.
• 11/2017Prof. Jie Gu gave a workshop talk at International Conerence on Computer Aided Design (ICCAD) Workshop, titled: "Let a Program Touch the Transistors: a Cross-layer Design Methodology for Co-design and Collaboration between Microprocessor and Mixed-Signal Circuits".
• 8/2017Prof. Jie Gu gave an invited talk at Midwest Symposium on Circuits and Systems (MWSCAS), titled: "Software-Guided Greybox Design Methodology with Integrated Power and Clock Management".
• 6/2017We delivered the world's fastest regulator running at 2GHz with a special resonant switching technique for Ultra-low Voltage/ Near-threshold Computing!
• 6/2017Tianyu Jia published the paper "A 0.3-0.86V Fully Integrated Buck Regulator with 2GHz Resonant Switching for Ultra-Low Power Applications", at 2017 Symposia on VLSI Technology and Circuits (Kyoto, Japan).
• 6/2017Tianyu Jia presented the paper "Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management", at Design Automation Conference (DAC) 2017.
• 5/2017Prof. Gu gave a talk in Greater Chicago Area System Research Workshop (GCASR).
• 1/2017Prof. Jie Gu presented the paper "Exploiting Accelerated Aging Effect for On-line Configurability and Hardware Tracking", at ASP-DAC 2017.
• 11/2016Prof. Jie Gu gave a talk at International Conerence on Computer Aided Design (ICCAD) Workshop, titled: "Switched Capacitor Regulator Modeling and Optimization for Instruction-based Ultra-fine Dynamic Voltage Scaling (IUDVS)".
• 10/2016Our first test chip "Emma" just came back in October and it works !!!
• 09/2016Kofi Otseidu joined the group as Ph.D. student.
• 08/2016Zhengyu Chen presented the Paper "Analysis and Design of Energy Efficient Timing domain signal processing" at ISLPED 2016.
• 08/2016Huanyu Wang presented the paper "Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design" at ISLPED 2016.
• 07/2016Tianyu Jia presented the paper "Exploration of Associative Power Management with Instruction Governed Operation for Ultra-low Power Design" at DAC 2016.